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| december 2009 doc id 16941 rev 1 1/47 47 lsm303dlh sensor module: 3-axis accelerometer an d 3-axis magnetometer features analog supply voltage: 2.5 v to 3.3 v digital supply voltage ios: 1.8 v power-down mode 3 magnetic field channels and 3 acceleration channels 1.3 to 8,1 gauss magnetic field full-scale 2 g /4 g /8 g dynamically selectable full- scale 16-bit data out i 2 c serial interface 2 independent programmable interrupt generators for free-fall and motion detection embedded self-test accelerometer sleep-to-wakeup function 6d orientation detection ecopack ? rohs and ?green? compliant (see section 10 ) applications compensated compassing map rotation position detection motion-activated functions free-fall detection intelligent power-saving for handheld devices display orientation gaming and virtual reality input devices impact recognition and logging vibration monitoring and compensation description the lsm303dlh is a system-in-package featuring a 3d digital linear acceleration sensor and a 3d digital magnetic sensor. the various sensing elements are manufactured using specialized micromachining processes, while the ic interfaces are realized using a cmos technology that allows the design of a dedicated circuit which is trimmed to better match the sensing element characteristics. the lsm303dlh has a linear acceleration full-scale of 2 g / 4 g / 8 g and a magnetic field full-scale of 1.3 / 1.9 / 2.5 / 4.0 / 4.7 / 5,6 / 8.1 gauss , both fully selectable by the user. the lsm303dlh includes an i 2 c serial bus interface that supports standard mode (100 khz) and fast mode (400 khz). the inte rnal self-test capability allows the user to check the functioning of the whole module in the final application. the system can be configured to generate an interrupt signal by inertial wakeup/free-fall events, as well as by the position of the device itself. thresholds and timing of interrupt generators are programmable on the fly by the end user. magnetic and accelerometer parts can be enabled or put in power-down mode separately. the lsm303dlh is available in a plastic land grid array (lga) package, and is guaranteed to operate over an extended temperature range from -30 to +85 c. table 1. device summary part number temp. range [c] package packing lsm303dlh -30 to +85 lga-28 tr ay LSM303DLHTR tape and reel lga-28l (5x5x1.0 mm) www.st.com obsolete product(s) - obsolete product(s)
contents lsm303dlh 2/47 doc id 16941 rev 1 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 module specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.1 accelerometer sensor i2c - inter ic control interface . . . . . . . . . . . . . . 14 2.3.2 magnetic field sensing i2c digital interface . . . . . . . . . . . . . . . . . . . . . . 15 3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 linear acceleration sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2 zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3 sleep-to-wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2 linear acceleration self-test operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.3 magnetic self-test operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 external capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2 pull-up resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.3 digital interface power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.4 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.5 high current wiring effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7 digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.1 i2c serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.1.1 i2c operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 obsolete product(s) - obsolete product(s) lsm303dlh contents doc id 16941 rev 1 3/47 7.1.2 linear acceleration digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.1.3 magnetic field digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9 registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.1 linear acceleration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.1.1 ctrl_reg1_a (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.1.2 ctrl_reg2_a (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.1.3 ctrl_reg3_a (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.1.4 ctrl_reg4_a (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.1.5 ctrl_reg5_a (24h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ) 33 9.1.6 hp_filter_reset_a (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.1.7 reference_a (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.1.8 status_reg_a(27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.1.9 out_x_l_a (28h), out_x_h_a (29h) . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.1.10 out_y_l_a (2ah), out_y_h_a (2bh) . . . . . . . . . . . . . . . . . . . . . . . . 34 9.1.11 out_z_l_a (2ch), out_z_h_a (2dh) . . . . . . . . . . . . . . . . . . . . . . . . 34 9.1.12 int1_cfg_a (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.1.13 int1_src_a (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.1.14 int1_ths_a (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.1.15 int1_duration_a (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.1.16 int2_cfg_a (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.1.17 int2_src_a (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.1.18 int2_ths_a (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.1.19 int2_duration_a (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.2 magnetic field sensing register description . . . . . . . . . . . . . . . . . . . . . . . 39 9.2.1 cra_reg_m (00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.2.2 crb_reg_m (01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.2.3 mr_reg_m (02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.2.4 out_x_m (03-04h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.2.5 out_y_m (05-06h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.2.6 out_z_m (07-08h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.2.7 sr_reg_m (09h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.2.8 ir_reg_m (0ah/0bh/0ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 obsolete product(s) - obsolete product(s) contents lsm303dlh 4/47 doc id 16941 rev 1 10 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 obsolete product(s) - obsolete product(s) lsm303dlh list of tables doc id 16941 rev 1 5/47 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 4. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 5. i2c slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 6. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 7. magnetic st (positive bias) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 8. operational mode and power supply for magnetic field sensing . . . . . . . . . . . . . . . . . . . . 21 table 9. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 10. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 11. transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 12. transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 13. transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 24 table 14. sad+read/write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 15. transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 25 table 16. sad+read/write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 17. register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 18. ctrl_reg1_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 19. ctrl_reg1_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 20. power mode and low-power output data rate configurations . . . . . . . . . . . . . . . . . . . . . . . 29 table 21. normal-mode output data rate configurations and low-pass cut-off frequencies . . . . . . . . 30 table 22. ctrl_reg2_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 23. ctrl_reg2_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 24. high-pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 25. high-pass filter cut-off frequency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 26. ctrl_reg3_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 27. ctrl_reg3_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 28. data signal on int 1 and int 2 pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 29. ctrl_reg4_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 30. ctrl_reg4_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 31. ctrl_reg5_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 32. ctrl_reg5_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 33. sleep-to-wake configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 34. reference_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 35. reference_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 36. status_reg_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 37. status_reg_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 38. int1_cfg_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 39. int1_cfg_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 40. interrupt 1 source configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 41. int1_src register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 42. int1_src_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 43. int1_ths register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 44. int1_ths description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 45. int1_duration_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 46. int2_duration_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 47. int2_cfg_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 48. int2_cfg_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 obsolete product(s) - obsolete product(s) list of tables lsm303dlh 6/47 doc id 16941 rev 1 table 49. interrupt mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 50. int2_src_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 51. int2_src_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 52. int2_ths register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 53. int2_ths description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 54. int2_duration_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 55. int2_duration_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 56. cra_reg_m register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 57. cra_reg_m description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 58. cra_reg m description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 59. cra_reg_m description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 60. cra_reg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 61. cra_reg description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 62. gain setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 63. mr_reg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 64. mr_reg description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 65. magnetic sensor operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 66. outxh_m register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 67. outxl_m register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 68. out_yh_m register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 69. out_yl_m register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 70. outzh_m register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 71. outzl_m register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 72. sr register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 74. ira_reg_m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 75. irb_reg_m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 76. irc_reg_m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 77. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 obsolete product(s) - obsolete product(s) lsm303dlh list of figures doc id 16941 rev 1 7/47 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3. i2c slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 4. lsm303dlh electrical connection 1 - recommended for i2c fast mode . . . . . . . . . . . . . . 20 figure 5. lsm303dlh electrical connection 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 figure 6. lga-28: mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 obsolete product(s) - obsolete product(s) block diagram and pin description lsm303dlh 8/47 doc id 16941 rev 1 1 block diagram and pin description 1.1 block diagram figure 1. block diagram # / . 4 2 / , , / ' ) # ) . 4 % 2 2 5 0 4 ' % . # , / # + 4 2 ) - - ) . ' # ) 2 # 5 ) 4 3 2 % & % 2 % . # % 3 % , & 4 % 3 4 9 : 9 : 8 8 - 5 8 3 $ ! ? ! 3 # , ? ! 3 $ ! ? - 3 # , ? - ) a # ( ! 2 ' % ! - 0 , ) & ) % 2 3 e n s i n g " l o c k 3 e n s i n g ) n t e r f a c e ! $ , o g i c c o n v e r t e r $ ) ) # 3 0 ) ) . 4 ) . 4 / & & 3 % 4 # ) 2 # 5 ) 4 3 " 5 ) , 4 ) . # ) 2 # 5 ) 4 3 - 5 8 ) ( # ( ! 2 ' % ! - 0 , ) & ) % 2 9 : 9 : 8 8 3 ! ? ! 3 % 4 2 % 3 % 4 ! - v # o n t r o l obsolete product(s) - obsolete product(s) lsm303dlh block diagram and pin description doc id 16941 rev 1 9/47 1.2 pin description figure 2. pin connection $ ) 2 % # 4 ) / . / & $ % 4 % # 4 ! " , % - ! ' . % 4 ) # & ) % , $ 3 9 8 : $ ) 2 % # 4 ) / . / & $ % 4 % # 4 ! " , % ! # # % , % 2 ! 4 ) / . 3 2 % 3 & ) , 4 6 $ $ 3 # , ? ! 2 % 3 & ) , 4 ) . 9 ' . $ " / 4 4 / - 6 ) % 7 . # 2 % 3 3 $ ! ? ! ) . 4 ) . 4 6 d d ? ) / ? ! . # 2 % 3 3 % 4 2 % 3 2 % 3 2 % 3 2 % 3 3 $ ! ? - 6 d d ? d i g ? - 3 # , ? - 2 % 3 3 % 4 6 $ $ $ 2 $ 9 ? - , 3 - $ , ( 3 ! ? ! 2 % 3 # 2 % 3 9 8 : ! - v obsolete product(s) - obsolete product(s) block diagram and pin description lsm303dlh 10/47 doc id 16941 rev 1 table 2. pin description pin# name function 1 reserved connect to gnd 2 gnd 0 v supply 3 reserved connect to gnd 4 sa0_a linear acceleration signal i 2 c less significant bit of the device address (sa0) 5 reserved to be connected to vdd i 2 c bus 6vddpower supply 7 reserved connect to vdd 8 nc not connected 9 nc not connected 10 reserved leave unconnected 11 reserved leave unconnected 12 set2 s/r capacitor connection (c2) 13 reserved leave unconnected 14 reserved leave unconnected 15 c1 reserved capacitor connection (c1) 16 set1 s/r capacitor connection (c2) 17 reserved connect to gnd 18 drdy_m magnetic signal interface data ready - test point 19 sda_m magnetic signal interface i 2 c serial data (sda) 20 scl_m magnetic signal interface i 2 c serial clock (scl) 21 vdd_dig_m magnetic sensor digital power supply 22 vdd_io_a linear acceleration signal interface power supply for i/o pins 23 reserved connect to vdd_io_a 24 scl_a linear acceleration signal interface i 2 c serial clock (scl) 25 sda_a linear acceleration signal interface i 2 c serial data (sda) 26 int1 inertial interrupt 1 27 int2 inertial interrupt 2 28 reserved connect to gnd obsolete product(s) - obsolete product(s) lsm303dlh module specifications doc id 16941 rev 1 11/47 2 module specifications 2.1 mechanical characteristics @ vdd = 2.5 v, t = 25 c unless otherwise noted (a) a. the product is factory calibrated at 2.5 v. the ope rational power supply range is from 2.5 v to 3.3 v. table 3. mechanical characteristics symbol parameter test conditions min. typ. (1) max. unit la_fs linear acceleration measurement range (2) fs bit set to 00 2.0 g fs bit set to 01 4.0 fs bit set to 11 8.0 m_fs magnetic measurement range gn bits set to 001 1.3 gauss gn bits set to 010 1.9 gn bits set to 011 2.5 gn bits set to 100 4.0 gn bits set to 101 4.7 gn bits set to 110 5.6 gn bits set to 111 8.1 la_so linear acceleration sensitivity fs bit set to 00 12 bit representation 0.911.1 m g /digit fs bit set to 01 12 bit representation 1.822.2 fs bit set to 11 12 bit representation 3.5 3.9 4.3 m_gn magnetic gain setting gn bits set to 001 (x,y) 1055 lsb/ gauss gn bits set to 001 (z) 950 gn bits set to 010 (x,y) 795 gn bits set to 010 (z) 710 gn bits set to 011 (x,y) 635 gn bits set to 011 (z) 570 gn bits set to 100 (x,y) 430 gn bits set to 100 (z) 385 gn bits set to 101 (x,y) 375 gn bits set to 101 (z) 335 gn bits set to 110 (x,y) 320 gn bits set to 110 (z) 285 gn bits set to 111 (2) (x,y) 230 gn bits set to 111 (2) (z) 205 obsolete product(s) - obsolete product(s) module specifications lsm303dlh 12/47 doc id 16941 rev 1 la_tcso linear acceleration sensitivity change vs. temperature fs bit set to 00 0.01 %/c la_tyoff linear acceleration typical zero- g level offset accuracy (3),(4) fs bit set to 00 20 m g la_tcoff linear acceleration zero- g level change vs temperature max delta from 25 c 0.1 m g /c la_an acceleration noise density fs bit set to 00 218 g / hz la_vst linear acceleration self-test output change (5),(6),(7) fs bit set to 00 x axis 300 lsb fs bit set to 00 y axis -300 lsb fs bit set to 00 z axis 350 lsb m_cas magnetic cross-axis sensitivity cross field = 0.5 gauss happlied = 3 gauss 1 %fs/ gauss m_ef maximum exposed field no permitting effect on zero reading 10000 gauss m_st magnetic self test positive bias mode, gn bits set to 100 on x, y axis 270 lsb positive bias mode, gn bits set to 100 on z axis 255 lsb m_r magnetic resolution vdd = 3 v 8 mgauss m_df disturbing field sensitivity starts to degrade. user s/r pulse to restore sensitivity 20 gauss top operating temperature range -30 +85 c 1. typical specificat ions are not guaranteed 2. verified by wafer level test and measur ement of initial offset and sensitivity 3. typical zero- g level offset value after msl3 preconditioning 4. offset can be eliminated by enabl ing the built-in high-pass filter 5. the sign of ?self-test output change? is defined by the ctrl_reg4 stsign bit ( table 29 ), for all axes. 6. self-test output changes with the power supply. ?self-test output change? is defined as output[lsb] (ctrl_reg4 st bit=1) - output[lsb] (ctrl_reg4 st bit=0) . 1lsb=4 g /4096 at 12bit representation, 2 g full-scale 7. output data reach 99% of final value after 1/odr+1ms when enabling self-test mode, due to device filtering table 3. mechanical characteristics (continued) symbol parameter test conditions min. typ. (1) max. unit obsolete product(s) - obsolete product(s) lsm303dlh module specifications doc id 16941 rev 1 13/47 2.2 electrical characteristics @ vdd = 2.5 v, t = 25 c unless otherwise noted. table 4. electrical characteristics symbol parameter test conditions min. typ. (1) max. unit vdd supply voltage 2.5 3.3 v vdd_io_a accelerometer module power supply for i/o 1.71 1.8 vdd+0.1 v vdd_dig_m magnetic module digital power supply 1.71 1.8 2.0 v vdd i2c bus magnetic module i 2 c bus power supply 1.71 1.8 vdd+0.1 v idd current consumption in normal mode (2) 0.83 ma iddpdn current consumption in power- down mode t = 25c 3 a top operating temperature range -30 +85 c 1. typical specificat ions are not guaranteed. 2. magnetic sensor setting odr = 7.5 hz. accelerometer sensor odr = 50 hz. obsolete product(s) - obsolete product(s) module specifications lsm303dlh 14/47 doc id 16941 rev 1 2.3 communication interface characteristics 2.3.1 accelerometer sensor i 2 c - inter ic control interface subject to general operating conditions for vdd and top. figure 3. i 2 c slave timing diagram (b) table 5. i 2 c slave timing values symbol parameter i 2 c standard mode (1) i 2 c fast mode (1) unit min max min max f (scl) scl clock frequency 0 100 0 400 khz t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0.01 3.45 0.01 0.9 s t r(sda) t r(scl) sda and scl rise time 1000 20 + 0.1c b (2) 300 ns t f(sda) t f(scl) sda and scl fall time 300 20 + 0.1c b (2) 300 t h(st) start condition hold time 4 0.6 s t su(sr) repeated start condition setup time 4.7 0.6 t su(sp) stop condition setup time 4 0.6 t w(sp:sr) bus free time between stop and start condition 4.7 1.3 1. data based on standard i 2 c protocol requirement, not tested in production. 2. cb = total capacitance of one bus line, in pf. b. measurement points are done at 0.2vdd_io and 0.8vdd_io, for both port. 6 ' $ 6 & / w i 6 ' $ w v x 6 3 w z 6 & / / w v x 6 ' $ w u 6 ' $ w v x 6 5 w k 6 7 w z 6 & / + w k 6 ' $ w u 6 & / w i 6 & / w z 6 3 6 5 6 7 $ 5 7 5 ( 3 ( $ 7 ( ' 6 7 $ 5 7 6 7 2 3 6 7 $ 5 7 obsolete product(s) - obsolete product(s) lsm303dlh module specifications doc id 16941 rev 1 15/47 2.3.2 magnetic field sensing i 2 c digital interface this magnetic sensor ic has a 7- bit serial address and supports i 2 c protocols with standard and fast modes (100 khz and 400 khz, respectively), but does not support high-speed mode (hs). external pull-up resistors are required to support the standard and fast modes. depending on the application, the internal pull-ups may be used to support slower data speeds than specified by i 2 c standards. this device does not contain 50 ns spike suppression, as required by fast mode operation in the i 2 c bus specification. activities required by the master (register read and write) have priority over internal activities, such as measurement. the purpose of this priority is to prevent the master waiting and the i 2 c bus being engaged for longer than necessary. obsolete product(s) - obsolete product(s) absolute maximum ratings lsm303dlh 16/47 doc id 16941 rev 1 3 absolute maximum ratings stresses above those listed as ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 6. absolute maximum ratings symbol ratings maximum value unit vin input voltage on any control pin (scl, sda) -0.3 to vdd_io +0.3 v a pow acceleration (any axis, powered, vdd = 2.5 v) 3,000 for 0.5 ms g 10,000 for 0.1 ms g a unp acceleration (any axis, unpowered) 3,000 for 0.5 ms g 10,000 for 0.1 ms g t op operating temperature range -30 to +85 c t stg storage temperature range -40 to +125 c this is a mechanical shock sensitive device, improper handling can cause permanent damages to the part. this is an esd sensitive device, improper handling can cause permanent damages to the part. obsolete product(s) - obsolete product(s) lsm303dlh terminology doc id 16941 rev 1 17/47 4 terminology 4.1 linear acceleration sensitivity linear acceleration sensitivity describes the gain of the accelerometer sensor and can be determined e.g. by applying 1 g acceleration to it. because the sensor can measure dc accelerations, this can be done easily by pointing the selected axis towards the ground, noting the output value, rotating the sensor 180 degrees (pointing towards the sky) and noting the output value again. by doing so, a 1 g acceleration is applied to the sensor. subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. this value changes very little over temperature and over time. the sensitivity tolerance describes the range of sensitivities of a large number of sensors. 4.2 zero- g level zero- g level offset (la_tyoff) describes the deviation of an actual output signal from the ideal output signal if no linear acceleration is present. a sensor in a steady state on a horizontal surface will measure 0 g on both the x and y axes, wh ereas the z axis will measure 1 g . ideally, the output is in the middle of the dynamic range of the sensor (content of out registers 00h, data expressed as 2?s complement number). a deviation from the ideal value in this case is called zero- g offset. offset is to some extent a result of stress to the mems sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. offset changes little over temperature; see ?linear acceleration zero- g level change vs temperature? (la_tcoff) in table 3. the zero- g level tolerance (tyoff) describes the standard deviation of the range of zero- g levels of a group of sensors. 4.3 sleep-to-wakeup the ?sleep-to-wakeup? function, in conjunction with low-power mode, allows further reduction of system power consumption and the development of new smart applications. the lsm303dlh may be set to a low-power operating mode, characterized by lower date rate refreshing. in this way the device, even if sleeping, continues sensing acceleration and generating interrupt requests. when the sleep-to-wakeup function is activated, the lsm303dlh is able to automatically wake up as soon as the interrupt event has been detected, increasing the output data rate and bandwidth. with this feature the system may be efficiently switched from low-power mode to full-performance depending on user-selectable positioning and acceleration events, thus ensuring power-saving and flexibility. obsolete product(s) - obsolete product(s) functionality lsm303dlh 18/47 doc id 16941 rev 1 5 functionality the lsm303dlh is a system-in-package featuring a 3d digital linear acceleration and 3d digital magnetic field detection sensor. the system includes specific sensing elements and an ic interfaces capable of measuring both the linear acceleration and magnetic field applied to it, and to provide a signal to the external world through an i 2 c serial interface with separated digital ouput. the sensing system is manufactured using specialized micromachining processes, while the ic interfaces are realized using a cmos technology that allows the design of a dedicated circuit which is trimmed to better match the sensing element characteristics. the lsm303dlh features two data-ready signals (rdy) which indicate when a new set of measured acceleration data and magnetic data are available, thus simplifying data synchronization in the digital system that uses the device. the lsm303dlh may also be configured to generate an inertial wakeup and free-fall interrupt signal according to a programmed acceleration event along the enabled axes. both free-fall and wakeup can be used simultaneously on two different accelerometer interrupts. 5.1 factory calibration the ic interface is factory calibrated for linea r acceleration sensitiv ity (la_so), and linear acceleration zero- g level (la_tyoff). the trimming values are stored inside the device in non-volatile memory. when the device is turned on, the trimming parameters are downloaded into the registers to be used during normal operation. this allows the use of the device without further calibration. 5.2 linear acceleratio n self-test operation self-test allows the checking of sensor functionality without moving it. the self-test function is off when the self-test bit (st) of ctrl_reg4_a (control register 4) is programmed to ?0?. when the self-test bit of ctrl_reg4_a is programmed to ?1? an actuation force is applied to the sensor, simulating a definite input acce leration. in this case the sensor outputs will exhibit a change in their dc levels which are related to the selected full-scale through the device sensitivity. when self-test is activate d, the device output level is given by the algebraic sum of the signals produced by the ac celeration acting on the sensor and by the electrostatic test-force. if the output signals change within the amplitude specified in table 3 , then the sensor is working properly and the parameters of the interface chip are within the defined specifications. 5.3 magnetic self-test operation to check the magnetic sensor for proper operation, a self-test feature is incorporated in which the sensor offset straps are excited to create a nominal field strength (bias field) to be measured. to implement this self-test, the least significant bits (ms1 and ms0) of configuration register a are changed from 00 to 01 (0x12 or 0b000xxx01). obsolete product(s) - obsolete product(s) lsm303dlh functionality doc id 16941 rev 1 19/47 by placing the mode register into single-c onversion mode (0x01), two data acquisition cycles are made on each magnetic vector. the first acquisition is a set pulse followed shortl y by measurement data of the external field. the second acquisition has the offset strap excited in the positive bias mode to create about a 0.6 gauss self-test field plus the external field. the first acquisition values are subtracted from the second acquisition, and the net me asurement is placed into the data output registers. to leave self-test mode, change the ms1 and ms0 bits of the configuration register a back to 0x00. also, change the mode register if single-conversion mode is not the intended next mode of operation. table 7. magnetic st (positive bias) symbol gn bits setting test axis min. typ. (1) 1. typical specificat ions are not guaranteed max. unit st_m gn bits set to 001 x,y axis 655 lsb z axis 630 gn bits set to 010 x,y axis 495 z axis 470 gn bits set to 011 x,y axis 395 z axis 375 gn bits set to 100 x,y axis 270 z axis 255 gn bits set to 101 x,y axis 235 z axis 225 gn bits set to 110 x,y axis 200 z axis 190 gn bits set to 111 (2) x,y axis 140 z axis 135 obsolete product(s) - obsolete product(s) application hints lsm303dlh 20/47 doc id 16941 rev 1 6 application hints figure 4. lsm303dlh electrical connection 1 - recommended for i 2 c fast mode figure 5. lsm303dlh electrical connection 2 $ ) 2 % # 4 ) / . 3 / & $ % 4 % # 4 ! " , % - ! ' . % 4 ) # & ) % , $ 3 $ ) 2 % # 4 ) / . 3 / & $ % 4 % # 4 ! " , % ! # # % , % 2 ! 4 ) / . 3 2 % 3 & ) , 4 6 $ $ 3 # , ? ! 2 % 3 & ) , 4 ) . 9 ' . $ 4 / 0 6 ) % 7 . # 2 % 3 3 $ ! ? ! ) . 4 ) . 4 6 d d ? ) / ? ! . # 2 % 3 6 $ $ 3 $ ! ? - 6 $ $ ? d i g ? - 3 # , ? - 3 % 4 2 % 3 $ 2 $ 9 ? - , 3 - $ , ( 3 ! 2 % 3 # # u & ' . $ # u & 6 d d ? ) / ? ! 6 d d ? d i g ? - 6 d d # u & # u & 9 8 : 9 8 : t o 6 d d ) # b u s ' . $ 3 % 4 2 % 3 2 % 3 2 % 3 6 d d ? ) # ? b u s 2 p u k / h m 2 p u ! - v $ i g i t a l s i g n a l f r o m t o s i g n a l c o n t r o l l e r 3 i g n a l s l e v e l s a r e d e f i n e d b y p r o p e r s e l e c t i o n o f 6 d d $ ) 2 % # 4 ) / . 3 / & $ % 4 % # 4 ! " , % - ! ' . % 4 ) # & ) % , $ 3 $ ) 2 % # 4 ) / . 3 / & $ % 4 % # 4 ! " , % ! # # % , % 2 ! 4 ) / . 3 2 % 3 & ) , 4 6 $ $ 3 # , ? ! 2 % 3 & ) , 4 ) . 9 ' . $ 4 / 0 6 ) % 7 . # 2 % 3 3 $ ! ? ! ) . 4 ) . 4 6 d d ? ) / ? ! . # 2 % 3 6 $ $ 3 $ ! ? - 6 $ $ ? d i g ? - 3 # , ? - 3 % 4 2 % 3 $ 2 $ 9 ? - , 3 - $ , ( 3 ! 2 % 3 # # u & ' . $ # u & 6 d d ? ) / ? ! 6 d d ? d i g ? - 6 d d # u & # u & 9 8 : 9 8 : t o p i n ' . $ 3 % 4 2 % 3 2 % 3 2 % 3 ! - v obsolete product(s) - obsolete product(s) lsm303dlh application hints doc id 16941 rev 1 21/47 6.1 external capacitors the c1 and c2 external capacitors should have a low sr value ceramic type construction. reservoir capacitor c1 is nominally 4.7 f in capacitance, with the set/reset capacitor c2 nominally 0.22 f in capacitance. the device core is supplied through the vdd line. power supply decoupling capacitors (c4=100 nf ceramic, c3=10 f al) should be placed as near as possible to the supply pin of the device (common design practice). all the voltage and ground supplies must be present at the same time to obtain proper behavior of the ic (refer to figure 4 ). the functionality of the device and the measured acceleration/magnetic field data is selectable and accessible through the i 2 c interface. the functions, the threshold and the timing of the two interrupt pins (int 1 and int 2) can be completely programmed by the user through the i 2 c interface. 6.2 pull-up resistors pull-up resistors are placed on the two i 2 c bus lines. 6.3 digital interface power supply this digital interface dedicated to the linear acceleration signal is capable of operating with a standard power supply (vdd) or using a dedicated power supply (vdd_io_a). this digital interface dedicated to the magne tic field signal requires a dedicated power supply (vdd_dig_m). the table below shows the modes available in the various power supply conditions. 6.4 soldering information the lga package is compliant with the ecopack ? , rohs and ?green? standard. it is qualified for soldering heat resist ance according to jedec j-std-020. leave ?pin 1 indicator? unconnected during soldering. land pattern and soldering recommendations are available at www.st.com/ table 8. operational mode and power supply for magnetic field sensing vdd_dig_m vdd mode supported description high high all except off digital i/o pins: range fr om gnd to vdd_i2c_bus / vdd_dig_m. device fully functional. digital logic blocks are powered from vdd_dig_m supply, including all onboard clocks. high low power down digital i/o pins: range fr om gnd to vdd_i2c_bus / vdd_dig_m. device measurement functionality not supported. device i 2 c bus and register access supported. obsolete product(s) - obsolete product(s) application hints lsm303dlh 22/47 doc id 16941 rev 1 6.5 high current wiring effects high current in wiring and printed circuit traces can be the cause of errors in magnetic field measurements for compassing. conducto-generated magnetic fields add to eart h?s magnetic field, creating errors in compass heading computation. keep currents that are higher than 10 ma a fe w millimeters further away from the sensor ic. obsolete product(s) - obsolete product(s) lsm303dlh digital interfaces doc id 16941 rev 1 23/47 7 digital interfaces the registers embedded inside the lsm303dlh are accessible through two separate i 2 c serial interfaces: one for the accelerometer core and the other for the magnetometer core. the two interfaces can be connected together on the pcb. 7.1 i 2 c serial interface the lsm303dlh i 2 c is a bus slave. the i 2 c is employed to write the data into the registers whose content can also be read back. the relevant i 2 c terminology is given in the table below. there are two signals associated with the i 2 c bus: the serial clock line (scl) and the serial data line (sda). the latter is a bidirectional line used for sending and receiving the data to/from the interface. table 9. serial interface pin description pin name pin description scl_a i 2 c serial clock (scl) for accelerometer sda_a i 2 c serial data (sda) for accelerometer scl_m i 2 c serial clock (scl) for magnetometer sda_m i 2 c serial data (sda) for magnetometer table 10. serial interface pin description term description transmitter the device which sends data to the bus receiver the device which receives data from the bus master the device which initiates a transfer, generates clock signals and terminates a transfer slave the device addressed by the master obsolete product(s) - obsolete product(s) digital interfaces lsm303dlh 24/47 doc id 16941 rev 1 7.1.1 i 2 c operation the transaction on the bus is started through a start (st) signal. a start condition is defined as a high to low transition on the data line while the scl line is held high. after this has been transmitted by the master, the bus is considered busy. the next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the 8th bit tells whether the master is receiving data from the slave or transmitting data to the slave. when an address is sent, each device in the system compares the first seven bits after a start condition with its address. if they match, the device considers itself addressed by the master. data transfer with acknowledge is mandatory. the transmitter must release the sda line during the acknowledge pulse. the receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock pulse. a receiver which has been addressed is obliged to generate an acknowledge after each byte of data received. the i 2 c embedded inside the lsm303dlh behaves like a slave device and the following protocol must be adhered to. after the start condition (st) a slave address is sent. once a slave acknowledge (sak) has been returned, an 8-bit sub-a ddress (sub) is transmitted: the 7 lsb represent the actual register address while the msb enables address auto-increment. if the msb of the sub field is ?1?, the sub (register address) is automatically increased to allow multiple data read/write. data are transmitted in byte format (data). each data transfer contains 8 bits. the number of bytes transferred per transfer is unlimited. data is transferred with the most significant bit (msb) first. if a receiver cannot receive another complete byte of data until it has performed some other function, it can hold the clock line scl low to force the transmitter into a wait state. data transfer only continues when the receiver is ready for another byte and releases the data line. if a slave receiver does not acknowledge the slave address (i.e. it is not able to receive because it is performing a real-time function) the data line must be left high by the slave. the master can then abort the transfer. a low to high transition on the sda line while the scl line is high is defined as a stop condition. each data transfer must be terminated by the generation of a stop (sp) condition. table 11. transfer when master is writing one byte to slave master st sad + w sub data sp slave sak sak sak table 12. transfer when master is writing multiple bytes to slave master st sad + w sub data data sp slave sak sak sak sak table 13. transfer when master is receiving (reading) one byte of data from slave master st sad + w sub sr sad + r nmak sp slave sak sak sak data obsolete product(s) - obsolete product(s) lsm303dlh digital interfaces doc id 16941 rev 1 25/47 7.1.2 linear accelera tion digital interface for linear acceleration, the default (factory) 7-bit slave address is 001100xb. the sdo / sa0 pad can be used to modify the least significant bit of the device address. if the sa0 pad is connected to voltage supply, lsb is ?1? (address 0011001b) otherwise if the sa0 pad is connected to ground, lsb value is ?0? (address 0011000b). this solution permits connecting and addressing two different accelerometers to the same i 2 c lines. the slave address is completed with a read/write bit. if the bit was ?1? (read), a repeated start (sr) condition will have to be issued after the two sub-addr ess bytes; if the bit is ?0? (write) the master transmits to the slave with direction unchanged. table 14 explains how the sad+read/write bit pattern is composed, listing all the possible configurations. table 14. sad+read/write patterns in order to read multiple bytes, it is necessary to assert the most significant bit of the sub- address field. in other words, sub(7) must be equal to 1 while sub(6-0) represents the address of the first register to be read. in the presented communication format , mak is master acknowledge and nmak is no master acknowledge. 7.1.3 magnetic fiel d digital interface the system communicates via a two-wire i 2 c bus system as a slave device. the interface protocol is defined by the i 2 c bus specification. the data rate is the standard mode 100 kbps or 400 kbps rates as defined by the i 2 c bus specifications. the bus bit format is an 8- bit data/address send and a 1-bit acknowledge bit. the format of the data bytes (payload) shall be case-sensitive ascii characters or bi nary data to the magnetic sensor slave, and binary data returned. negative binary values will be in two?s complement form. for magnetic sensor, the default (factory) 7-bit slave address is 0011110b (0x3c) for write operations, or 00111101b (0x3d) for read operations. the serial clock (scl_m) and serial data (sda_m) lines have optional internal pull-up resistors, but require resistive pull-up (rp) between the master device (usually a host microprocessor) and the lsm303dlh. pull-up resistance values of about 10 k ? are recommended with a nominal 1.8 v digital supply voltage (vdd_dig_m). command sad[6:1] sad[0] = sa0 r/w sad+r/w read 001100 0 1 00110001 (31h) write 001100 0 0 00110000 (30h) read 001100 1 1 00110011 (33h) write 001100 1 0 00110010 (32h) table 15. transfer when master is receiving (reading) multiple bytes of data from slave master st sad +w sub sr sad +r mak mak nmak sp slave sak sak sak data data data obsolete product(s) - obsolete product(s) digital interfaces lsm303dlh 26/47 doc id 16941 rev 1 the scl_m and sda_m lines in this bus specification can be connected to a host of devices. the bus can be a single master to multiple slaves, or it can be a multiple master configuration. all data transfers are initiated by the master device which is responsible for generating the clock signal, and the data transfers are 8 bits long. all devices are addressed by the unique 7-bit address of the i 2 c. after each 8-bit transfer, the master device generates a 9th clock pulse, and releases the sda_m line. the receiving device (addressed slave) pulls the sda_m line low to acknowledge (ack) the successful transfer, or leaves the sda_m high to negative acknowledge (nack). as per the i 2 c specification, all transitions in the sda_ m line must occur when scl_m is low. this requirement leads to two unique conditions on the bus associated with the sda_m transitions when scl_m is high. the master device pulling the sda line low while the scl_m line is high indicates the start (s) condition, while the stop (p) condition is indicated by the sda_m line pulled high while the scl_m line is high. the i 2 c protocol also allows for the restart condition, in which the master devi ce issues a second start condition without issuing a stop. all bus transactions begin with the master device issuing the start sequence followed by the slave address byte. the address byte contains the slave address; the upper 7 bits (bits7-1), and the least significant bit (lsb). the lsb of th e address byte designates if the operation is a read (lsb=1) or a write (lsb=0). at the 9th clock pulse, the receiving slave device issues the ack (or nack). following these bus events, the master sends data bytes for a write operation, or the slave clocks out data with a read operation. all bus transactions are terminated with the master issuing a stop sequence. i 2 c bus control can be implemented with either hardware logic or in software. typical hardware designs release the sda_m and scl_m lines as appropriate to allow the slave device to manipulate these lines. in a software implementation, care must be taken to perform these tasks in code. magnetic signal interface reading/writing the interface uses an address pointer to indicate which register location is to be read from or written to. these pointer locations are sent from the master to this slave device and succeed the 7-bit address plus 1 bit read/write identifier. to minimize the communication between the ma ster and magnetic digital interface of the lsm303dlh, the address pointer is updated automatically without master intervention. this automatic address pointer update has two additional features. first, when address 12 or higher is accessed the pointer updates to address 00, and secondly when address 09 is reached, the pointer rolls back to address 03. logically, the address pointer operation functions as shown below. if address pointer = 09, then address pointer = 03 while if address pointer > 12, then address pointer = 0 while address pointer = address pointer + 1 the address pointer value itself cannot be read via the i 2 c bus. any attempt to read an invalid address location returns 0?s, and any write to an invalid address location or an undefined bit within a valid address location is ignored by this device. table 16. sad+read/write patterns command sad[6:0] r/w sad+r/w read 0011110 1 00111101 (3dh) write 0011110 0 00111100 (3ch) obsolete product(s) - obsolete product(s) lsm303dlh register mapping doc id 16941 rev 1 27/47 8 register mapping the tables given below provide a listing of the 8-bit registers embedded in the device and the related addresses: table 17. register address map name slave address type register address default comment hex binary reserved (do not modify) 00 - 1f reserved ctrl_reg1_a tab.13 rw 20 010 0000 00000111 ctrl_reg2_a tab.13 rw 21 010 0001 00000000 ctrl_reg3_a tab.13 rw 22 010 0010 00000000 ctrl_reg4_a tab.13 rw 23 010 0011 00000000 ctrl_reg5_a tab.13 rw 24 010 0100 00000000 hp_filter_reset_a tab.13 r 2 5 010 0101 dummy register reference_a tab.13 rw 26 010 0110 00000000 status_reg_a tab.13 r 27 010 0111 00000000 out_x_l_a tab.13 r 28 010 1000 output out_x_h_a tab.13 r 29 010 1001 output out_y_l_a tab.13 r 2a 010 1010 output out_y_h_a tab.13 r 2b 010 1011 output out_z_l_a tab.13 r 2c 010 1100 output out_z_h_a tab.13 r 2d 010 1101 output reserved (do not modify) 2e - 2f reserved int1_cfg_a tab.13 rw 30 011 0000 00000000 int1_source_a tab.13 r 31 011 0001 00000000 int1_ths_a tab.13 rw 32 011 0010 00000000 int1_duration_a tab.13 rw 33 011 0011 00000000 int2_cfg_a tab.13 rw 34 011 0100 00000000 int2_source_a tab.13 r 35 011 0101 00000000 int2_ths_a tab.13 rw 36 011 0110 00000000 int2_duration_a tab.13 rw 37 011 0111 00000000 reserved (do not modify) 38 - 3f reserved cra_reg_m tab.15 rw 00 00000000 00010000 crb_reg_m tab.15 rw 01 00000001 00100000 mr_reg_m tab.15 rw 02 00000010 00000011 out_x_h_m tab.15 r 03 00000011 output obsolete product(s) - obsolete product(s) register mapping lsm303dlh 28/47 doc id 16941 rev 1 registers marked as reserved must not be changed. writing to these registers may cause permanent damage to the device. the content of the registers that are loaded at boot should not be changed. they contain the factory calibrated values. their content is automatically restored when the device is powered up. out_x_l_m tab.15 r 04 00000100 output out_y_h_m tab.15 r 05 00000101 output out_y_l_m tab.15 r 06 00000110 output out_z_h_m tab.15 r 07 00000111 output out_z_l_m tab.15 r 08 00001000 output sr_reg_mg tab.15 r 09 00001001 00000000 ira_reg_m tab.15 r 0a 00001010 01001000 irb_reg_m tab.15 r 0b 00001011 00110100 irc_reg_m tab.15 r 0c 00001100 00110011 table 17. register address map (continued) name slave address type register address default comment hex binary obsolete product(s) - obsolete product(s) lsm303dlh registers description doc id 16941 rev 1 29/47 9 registers description the device contains a set of registers which are used to control its behavior and to retrieve acceleration data. the register address, composed of 7 bits, is used to identify them and to write the data through the serial interface. 9.1 linear acceleration register for linear acceleration sensors, the default (factory) 7-bit slave address is 001100xb. 9.1.1 ctrl_reg1_a (20h) pm bits allow selection between power-down and two operating active modes. the device is in power-down mode when the pd bits are set to ?000? (default value after boot). table 20 shows all the possible power mode configurations and respective output data rates. output data in the low-power modes are computed with a low-pass filter cut-off frequency defined by dr1, dr0 bits. dr bits, in the normal-mode operation, select the data rate at which acceleration samples are produced. in low-power mode they define the output data resolution. table 21 shows all the possible configurations for the dr1 and dr0 bits. table 18. ctrl_reg1_a register pm2 pm1 pm0 dr1 dr0 zen yen xen table 19. ctrl_reg1_a description pm2 - pm0 power mode selection. default value: 000 (000: power-down; others: refer to table 20 ) dr1, dr0 data rate selection. default value: 00 (00:50 hz; others: refer to table 21 ) zen z axis enable. default value: 1 (0: z axis disabled; 1: z axis enabled) ye n y axis enable. default value: 1 (0: y axis disabled; 1: y axis enabled) xen x axis enable. default value: 1 (0: x axis disabled; 1: x axis enabled) table 20. power mode and low-power output data rate configurations pm2 pm1 pm0 power mode selection output data rate [hz] odr lp 0 0 0 power-down -- 0 0 1 normal mode odr obsolete product(s) - obsolete product(s) registers description lsm303dlh 30/47 doc id 16941 rev 1 9.1.2 ctrl_reg2_a (21h) the boot bit is used to refresh the content of internal registers stored in the flash memory block. at device power-up, the content of the flash memory block is transferred to the 0 1 0 low-power 0.5 0 1 1 low-power 1 1 0 0 low-power 2 1 0 1 low-power 5 1 1 0 low-power 10 table 21. normal-mode output data rate configurations and low-pass cut-off frequencies dr1 dr0 output data rate [hz] odr low-pass filter cut-off frequency [hz] 00 50 37 01 100 74 1 0 400 292 1 1 1000 780 table 20. power mode and low-power output data rate configurations (continued) pm2 pm1 pm0 power mode selection output data rate [hz] odr lp table 22. ctrl_reg2_a register boot hpm1 hpm0 fds hpen2 hpen1 hpcf1 hpcf0 table 23. ctrl_reg2_a description boot reboot memory content. default value: 0 (0: normal mode; 1: reboot memory content) hpm1, hpm0 high-pass filter mode selection. default value: 00 (00: normal mode; others: refer to table 24 ) fds filtered data selection. default value: 0 (0: internal filter bypassed; 1: data from internal filter sent to output register) hpen2 high-pass filter enabled for interrupt 2 source. default value: 0 (0: filter bypassed; 1: filter enabled) hpen1 high-pass filter enabled for interrupt 1 source. default value: 0 (0: filter bypassed; 1: filter enabled) hpcf1, hpcf0 high-pass filter cut-off frequency c onfiguration. default value: 00 (00: hpc=8; 01: hpc=16; 10: hpc=32; 11: hpc=64) obsolete product(s) - obsolete product(s) lsm303dlh registers description doc id 16941 rev 1 31/47 internal registers related to trimming functions to permit good device behavior. if, for any reason, the content of the trimming registers was changed, it is sufficient to use this bit to restore the correct values. when the boot bit is set to ?1? the content of internal flash is copied to the corresponding internal registers and is used to calibrate the device. these values are factory-trimmed and are different for every accelerometer. they permit good device behavior and normally do not have to be modified. at the end of the boot process, the boot bit is again set to ?0?. hpcf[1:0] . these bits are used to configure the high-pass filter cut-off frequency f t ,which is given by: the equation can be simplified to the following approximated equation: 9.1.3 ctrl_reg3_a (22h) table 24. high-pass filter mode configuration hpm1 hpm0 high-pass filter mode 0 0 normal mode (reset reading hp_reset_filter) 0 1 reference signal for filtering 1 0 normal mode (reset reading hp_reset_filter) table 25. high-pass filter cut-off frequency configuration hpcoeff2,1 f t [hz] data rate = 50 hz f t [hz] data rate = 100 hz f t [hz] data rate = 400 hz f t [hz] data rate = 1000 hz 00 1 2 8 20 01 0.5 1 4 10 10 0.25 0.5 2 5 11 0.125 0.25 1 2.5 f t 1 1 hpc ----------- - ? ?? ?? f s 2 ------ ? ln = f t f s 6hpc ? ---------------------- = table 26. ctrl_reg3_a register ihl pp_od lir2 i2_cfg1 i2_cfg0 lir1 i1_cfg1 i1_cfg0 obsolete product(s) - obsolete product(s) registers description lsm303dlh 32/47 doc id 16941 rev 1 9.1.4 ctrl_reg4_a (23h) table 27. ctrl_reg3_a description ihl interrupt active high, low. default value: 0 (0: active high; 1:active low) pp_od push-pull/open drain selection on interrupt pad. default value 0. (0: push-pull; 1: open drain) lir2 latch interrupt request on int2_src register, with int2_src register cleared by reading int2_src itself. default value: 0. (0: interrupt request not latched; 1: interrupt request latched) i2_cfg1, i2_cfg0 data signal on int 2 pad control bits. default value: 00. (see table below) lir1 latch interrupt request on int1_src register, with int1_src register cleared by reading int1_src register. default value: 0. (0: interrupt request not latched; 1: interrupt request latched) i1_cfg1, i1_cfg0 data signal on int 1 pad control bits. default value: 00. (see table below) table 28. data signal on int 1 and int 2 pad i1(2)_cfg1 i1(2)_cfg0 int 1(2) pad 0 0 interrupt 1 (2) source 0 1 interrupt 1 source or interrupt 2 source 1 0 data ready 1 1 boot running table 29. ctrl_reg4_a register bdu ble fs1 fs0 stsign 0 st --- table 30. ctrl_reg4_a description bdu block data update. default value: 0 (0: continuos update; 1: output register s not updated between msb and lsb reading) ble big/little endian data selection. default value 0. (0: data lsb @ lower address; 1: data msb @ lower address) fs1, fs0 full-scale selection. default value: 00. (00: 2 g ; 01: 4 g ; 11: 8 g ) stsign self-test sign. default value: 00. (0: self-test plus; 1 self-test minus) st self-test enable. default value: 0. (0: self-test disabled; 1: self-test enabled) obsolete product(s) - obsolete product(s) lsm303dlh registers description doc id 16941 rev 1 33/47 the bdu bit is used to inhibit output register updates between the reading of the upper and lower register parts. in default mode (bdu = ?0?), the lower and upper register parts are updated continuously. if it is not certain to read faster than output data rate, it is recommended to set bdu bit to ?1?. in this way, after the reading of the lower (upper) register part, the content of that output register is not updated until the upper (lower) part is read also. this feature avoids reading lsb and msb related to different samples. 9.1.5 ctrl_reg5_a (24h) turnon bits are used for turning on the sleep-to-wake function. by setting the turnon [1:0] bits to 11, the ?sleep-to-wake? function is enabled. when an interrupt event occurs, the device goes into normal mode, increasing the odr to the value defined in ctrl_reg1_a. although the device is in normal mode, ctrl_reg1_a content is not automatically changed to ?normal mode? configuration. 9.1.6 hp_filter_reset_a (25h) dummy register. reading at this address instantaneously zeroes the content of the internal high-pass filter. if the high-pass filter is enabled, all three axes are instantaneously set to 0 g. this makes it possible to surmount the settling time of the high-pass filter. 9.1.7 reference_a (26h) table 31. ctrl_reg5_a register 000000turnon1turnon0 table 32. ctrl_reg5_a description tu r n o n 1 , tu r n o n 0 turn-on mode selection for sleep-to-wake function. default value: 00. table 33. sleep-to-wake configuration turnon1 turnon0 sl eep-to-wake status 0 0 sleep-to-wake function is disabled 11 turned on: the device is in low-power mode (odr is defined in ctrl_reg1_a) table 34. reference_a register ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 table 35. reference_a description ref7 - ref0 reference value for high-pass filter. default value: 00h. obsolete product(s) - obsolete product(s) registers description lsm303dlh 34/47 doc id 16941 rev 1 this register sets the acceleration value taken as a reference for the high-pass filter output. when the filter is turned on (at least one fds, hpen2, or hpen1 bit is equal to ?1?) and hpm bits are set to ?01?, filter out is generated taking this value as a reference. 9.1.8 status_reg_a(27h) 9.1.9 out_x_l_a (28h ), out_x_h_a (29h) x-axis acceleration data. the value is expressed as two?s complement. 9.1.10 out_y_l_a (2ah ), out_y_h_a (2bh) y-axis acceleration data. the value is expressed as two?s complement. 9.1.11 out_z_l_a (2ch), out_z_h_a (2dh) z-axis acceleration data. the value is expressed as two?s complement. table 36. status_reg_a register zyxor zor yor xor zyxda zda yda xda table 37. status_reg_a description zyxor x, y and z axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data has overwritten the pr evious one before it was read) zor z axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the z-axis ha s overwritten the previous one) yor y axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the y-axis has overwritten the previous one) xor x axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the x-axis has overwritten the previous one) zyxda x, y and z axis new data available. default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) zda z axis new data available. default value: 0 (0: new data for the z-axis is not yet available; 1: new data for the z-axis is available) yda y axis new data available. default value: 0 (0: new data for the y-axis is not yet available; 1: new data for the y-axis is available) xda x axis new data available. default value: 0 (0: new data for the x-axis is not yet available; 1: new data for the x-axis is available) obsolete product(s) - obsolete product(s) lsm303dlh registers description doc id 16941 rev 1 35/47 9.1.12 int1_cfg_a (30h) configuration register for interrupt 1 source. table 38. int1_cfg_a register aoi 6d zhie zlie yhie ylie xhie xlie table 39. int1_cfg_a description aoi and/or combination of interrupt events. default value: 0. (see table 40 ) 6d 6 direction detection function enable. default value: 0. (see table 40 ) zhie enable interrupt generation on z high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) zlie enable interrupt generation on z low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) yhie enable interrupt generation on y high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) ylie enable interrupt generation on y low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) xhie enable interrupt generation on x high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) xlie enable interrupt generation on x low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) table 40. interrupt 1 source configurations aoi 6d interrupt mode 0 0 or combination of interrupt events 0 1 6 direction move ment recognition 1 0 and combination of interrupt events 1 1 6 direction position recognition obsolete product(s) - obsolete product(s) registers description lsm303dlh 36/47 doc id 16941 rev 1 9.1.13 int1_src_a (31h) interrupt 1 source register. read-only register. reading at this address clears int1_src_a ia bit (and the interrupt signal on int 1 pin) and allows the refreshing of data in the int1_src_a register if the latched option was chosen. 9.1.14 int1_ths_a (32h) 9.1.15 int1_duration_a (33h) table 41. int1_src register 0 ia zhzlyhylxhxl table 42. int1_src_a description ia interrupt active. default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) zh z high. default value: 0 (0: no interrupt, 1: z high event has occurred) zl z low. default value: 0 (0: no interrupt; 1: z low event has occurred) yh y high. default value: 0 (0: no interrupt, 1: y high event has occurred) yl y low. default value: 0 (0: no interrupt, 1: y low event has occurred) xh x high. default value: 0 (0: no interrupt, 1: x high event has occurred) xl x low. default value: 0 (0: no interrupt, 1: x low event has occurred) table 43. int1_ths register 0 ths6 ths5 ths4 ths3 ths2 ths1 ths0 table 44. int1_ths description ths6 - ths0 interrupt 1 threshold. default value: 000 0000 table 45. int1_duration_a register 0 d6d5d4d3d2d1d0 table 46. int2_duration_a description d6 - d0 duration value. default value: 000 0000 obsolete product(s) - obsolete product(s) lsm303dlh registers description doc id 16941 rev 1 37/47 the d6 - d0 bits set the minimum duration of the interrupt 2 event to be recognized. duration steps and maximum values depend on the odr chosen. 9.1.16 int2_cfg_a (34h) configuration register for interrupt 2 source. table 47. int2_cfg_a register aoi 6d zhie zlie yhie ylie xhie xlie table 48. int2_cfg_a description aoi and/or combination of interrupt events. default value: 0. (see table below) 6d 6 direction detection function enable. default value: 0. (see table below) zhie enable interrupt generation on z high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) zlie enable interrupt generation on z low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) yhie enable interrupt generation on y high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) ylie enable interrupt generation on y low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) xhie enable interrupt generation on x high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) xlie enable interrupt generation on x low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) table 49. interrupt mode configuration aoi 6d interrupt mode 0 0 or combination of interrupt events 0 1 6 direction move ment recognition 1 0 and combination of interrupt events 1 1 6 direction position recognition obsolete product(s) - obsolete product(s) registers description lsm303dlh 38/47 doc id 16941 rev 1 9.1.17 int2_src_a (35h) interrupt 2 source register. read-only register. reading at this address clears int2_src_a ia bit (and the interrupt signal on int 2 pin) and allows the refreshing of data in the int2_src_a register if the latched option was chosen. 9.1.18 int2_ths_a (36h) 9.1.19 int2_duration_a (37h) table 50. int2_src_a register 0 ia zhzlyhylxhxl table 51. int2_src_a description ia interrupt active. default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) zh z high. default value: 0 (0: no interrupt, 1: z high event has occurred) zl z low. default value: 0 (0: no interrupt; 1: z low event has occurred) yh y high. default value: 0 (0: no interrupt, 1: y high event has occurred) yl y low. default value: 0 (0: no interrupt, 1: y low event has occurred) xh x high. default value: 0 (0: no interrupt, 1: x high event has occurred) xl x low. default value: 0 (0: no interrupt, 1: x low event has occurred) table 52. int2_ths register 0 ths6 ths5 ths4 ths3 ths2 ths1 ths0 table 53. int2_ths description ths6 - ths0 interrupt 1 threshold. default value: 000 0000 table 54. int2_duration_a register 0 d6d5d4d3d2d1d0 table 55. int2_duration_a description d6 - d0 duration value. default value: 000 0000 obsolete product(s) - obsolete product(s) lsm303dlh registers description doc id 16941 rev 1 39/47 the d6 - d0 bits set the minimum duration of the interrupt 2 event to be recognized. duration time steps and maximum values depend on the odr chosen. 9.2 magnetic field sensing register description the magnetometer core contains a set of registers which are used to control its behavior and to retrieve magnetic field data. the regist er?s address, composed of 8 bits, is used to identify them and to read/write the data through the serial interface. for magnetic field sensing interface, the default (factory) 7-bit slave address is 00111100b (0x3c) for write operations, or 00111101b (0x3d) for read operations. 9.2.1 cra_reg_m (00h) the configuration register a is used to configure the device for setting the data output rate and measurement configuration. cra0 through cra7 indicate bit locations, with cra denoting the bits that are in the configuration register. cra7 denotes the first bit of the data stream. the number in parentheses indicates the default value of that bit. table 56. cra_reg_m register 0 0 0 do2do1do0ms1ms0 table 57. cra_reg_m description cra7 to cra5 these bits must be cleared for correct operation. do2 to do0 data output rate bits. these bits set the rate at which data is written to all three data output registers ms1 to ms0 measurement configuration bits. these bi ts define the measurement flow of the device, specifically whether or not to inco rporate an applied bias to the sensor into the measurement table 58. cra_reg m description do2 do1 do0 minimum data output rate (hz) 00 0 0.75 00 1 1.5 01 0 3.0 01 1 7.5 10 0 15 10 1 30 11 0 75 1 1 1 not used obsolete product(s) - obsolete product(s) registers description lsm303dlh 40/47 doc id 16941 rev 1 9.2.2 crb_reg_m (01h) the configuration register b for setting the device gain. crb0 through crb7 indicate bit locations, with crb denoting the bits that are in the configuration register. crb7 denotes the first bit of the data stream. the number in parentheses indicates the default value of that bit. 9.2.3 mr_reg_m (02h) the mode register is an 8-bit register from which data can be read or to which data can be written. this register is used to select the operating mode of the device. mr0 through mr7 indicate bit locations, with mr denoting the bits that are in the mode register. mr7 denotes table 59. cra_reg_m description ms1 ms0 magnetic sensor operating mode 00 normal measurement configuration (default). in normal measurement configuration the device follows normal measurement flow. 0 1 positive bias configuration. 1 0 negative bias configuration. 1 1 this configuration is not used table 60. cra_reg register gn2 gn1 gn0 0 0 0 0 0 table 61. cra_reg description crb7 to crb5 gain configuration bits. these bits conf igure the gain for the device. the gain configuration is common for all channels crb7 to crb5 this bit must be cleared for correct operation table 62. gain setting gn2 gn1 gn0 sensor input field range [gauss] gain x/y and z [lsb/gauss] gain z [lsb/gauss] output range 001 1.3 1055 950 0xf800?0x07ff (-2048?2047) 0 1 0 1.9 795 710 0 1 1 2.5 635 570 1 0 0 4.0 430 385 1 0 1 4.7 375 335 1 1 0 5.6 320 285 1 1 1 8.1 230 205 obsolete product(s) - obsolete product(s) lsm303dlh registers description doc id 16941 rev 1 41/47 the first bit of the data stream. the number in parentheses indicates the default value of that bit. 9.2.4 out_x_m (03-04h) the data output x registers are two 8-bit registers, data output register h and data output register l. these registers store the measurement result from channel x. data output x register h contains the msb from the measurement result, and data output x register l contains the lsb from the measurement result. the value stored in these two registers is a 16-bit value in 2?s complement form, whose range is 0xf800 to 0x07ff. dxrh0 through dxrh7 and dxrl0 through dxrl7 indicate bit locations, with dxrh and dxrl denoting the bits that are in the data output x registers. dxrh7 and dxrl7 denote the first bit of the data stream. in the event the adc reading overflows or underflows for the given channel, or if there is a math overflow during the bias measurement, this da ta register will contai n the value -4096 in 2?s complement form. this register value clears after the next valid measurement is made . the content of this register is the msb magnetic field data for x-axis. table 63. mr_reg 000000md1md0 table 64. mr_reg description mr7 to mr2 these bits must be cleared for correct operation mr1 to mr0 mode select bits. these bits se lect the operation mode of this device. table 65. magnetic sensor operating mode md1 md0 mode 00 continuous-conversion mode: the device continuously performs conversions and places the result in the data register. rdy goes high when new data is placed in all three registers. after a power-on or a write to the mode or configuration register, the first measurement set is available from all three data output registers after a period of 2/ fdo, and subsequent measurements are available at a frequency of fdo, wher e fdo is the frequency of data output. 01 single-conversion mode: the device performs a single measurement, sets rdy high and returns to sleep mode. mode register returns to sleep mode bit values. the measurement remains in the data output register and rdy remains high until the data output register is read or another conversion is performed. 10-- 1 1 sleep mode. device is placed in sleep mode table 66. outxh_m register dxrh7 dxrh6 dxrh5 dxrh4 dxrh3 dxrh2 dxrh1 dxrh0 obsolete product(s) - obsolete product(s) registers description lsm303dlh 42/47 doc id 16941 rev 1 the content of this register is the lsb magnetic field data for x-axis. 9.2.5 out_y_m (05-06h) the data output y registers are two 8-bit registers, data output register h and data output register l. these registers store the measurement result from channel y. data output y register h contains the msb from the measurement result, and data output y register l contains the lsb from the measurement result. the content of this register is the msb magnetic field data for y-axis. the content of this register is the lsb magnetic field data for y-axis. 9.2.6 out_z_m (07-08h) the data output z registers are two 8-bit registers, data output register h and data output register l. these registers store the measurement result from channel z. data output z register h contains the msb from the measurement result, and data output z register l contains the lsb from the measurement result. the content of this register is the msb magnetic field data for z-axis. the content of this register is the lsb magnetic field data for z-axis. 9.2.7 sr_reg_m (09h) when one or more of the output registers are read, new data cannot be placed in any of the output data registers until all six data output registers are read. this requirement also table 67. outxl_m register dxrl7 dxrl6 dxrl5 dxrl4 dxrl3 dxrl2 dxrl1 dxrl0 table 68. out_yh_m register dyrh7 dyrh6 dyrh5 dyrh4 dyrh3 dyrh2 dyrh1 dyrh0 table 69. out_yl_m register dyrl7 dyrl6 dyrl5 dyrl4 dyrl3 dyrl2 dyrl1 dyrl0 table 70. outzh_m register dzrh7 dzrh6 dzrh5 dzrh4 dzrh3 dzrh2 dzrh1 dzrh0 table 71. outzl_m register dzrl7 dzrl6 dzrl5 dzrl4 dzrl3 dzrl2 dzrl1 dzrl0 obsolete product(s) - obsolete product(s) lsm303dlh registers description doc id 16941 rev 1 43/47 impacts drdy and rdy, which cannot be cleared until new data is placed in all the output registers. status register the status register (sr) is an 8-bit read-only register. this register is used to indicate device status. sr0 through sr7 indicate bit locations, with sr denoting the bits that are in the status register. sr7 denotes the first bit of the data stream. 9.2.8 ir_reg_m (0ah/0bh/0ch) the identification registers (ir) are used to identify the device. ir0 through ir7 indicate bit locations, with ira/irb/irc denoting the bits that are in the identification registers a, b & c. ira7/irb7/irc7 denotes the first bit of the data stream. the identification value for this device is stored in this register. this is a read-only register. register values. ascii value h table 72. sr register 00000renlocrdy table 73. status register bit designations md1 md0 mode sr7 to sr3 0 these bits must be cleared for correct operation sr2 ren regulator enabled bit. this bit is set when the internal voltage regulator is enabled. this bit is cleared when the internal regulator is disabled. sr1 lock data output register lock. this bit is set when some, but not all, of the six data output registers have been read. when this bit is set, the six data output registers are locked and any ne w data is not placed in these registers until one of four conditions are met: one, all six have been read or the mode changed, two, a por is issu ed, three, the mode is changed, or four, the measurement is changed. sr0 rdy ready bit. set when data is written to all six data registers. cleared when the device initiates a write to the data output registers, when in off mode, and after one or more of the data out put registers are written to. when rdy bit is clear, it shall remain cleared for a minimum of 5 s. the drdy pin can be used as an alternative to the status register for monitoring the device for conversion data. table 74. ira_reg_m 01001000 table 75. irb_reg_m 00110100 obsolete product(s) - obsolete product(s) registers description lsm303dlh 44/47 doc id 16941 rev 1 table 76. irc_reg_m 00110011 obsolete product(s) - obsolete product(s) lsm303dlh package information doc id 16941 rev 1 45/47 10 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com. ecopack is an st trademark. figure 6. lga-28: mechanical data and package dimensions dimensions ref. mm min. typ. max. a1 1 a2 0.785 a3 0.200 d1 4.850 5.000 5.150 e1 4.850 5.000 5.150 l1 1.650 l2 3.300 n1 0.550 m 0.040 0.100 0.160 t1 0.260 0.300 0.340 t2 0.360 0.400 0.440 d 0.200 k 0.050 h 0.100 lga-28 (5x5x1) land grid array packages outline and 8192208_b mechanical data obsolete product(s) - obsolete product(s) revision history lsm303dlh 46/47 doc id 16941 rev 1 11 revision history table 77. document revision history date revision changes 18-dec-2009 1 first issue. obsolete product(s) - obsolete product(s) lsm303dlh doc id 16941 rev 1 47/47 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2009 stmicroelectronics - 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